1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, this invention pertains to a semiconductor memory device in which a bit line formed in a memory cell is constituted by a semiconductor layer.
2. Description of the Related Art
The following has been presented as a semiconductor memory device having memory cells with a bit line formed by a semiconductor layer:
A TRENCH TRANSISTOR CROSS-POINT DRAM CELL W. F. RICHARDSON ET AL. IEDM85. p714-p717.
The disclosed DRAM cell has a trench on a silicon substrate, with a storage node formed in the trench. A storage dielectric is formed between the storage node and the substrate. Part of the storage node is connected to the substrate. An insulating film is formed on the exposed face of the storage node to isolate the storage node from a word line. The word line, which is so formed as to come into the trench, serves as a gate to a channel in the substrate along the side wall of the trench. Further, an n.sup.+ type diffused bit line is formed in the direction normal to the plane containing the word line.
With the above structure, as each memory cell is formed at the cross point between the word line and bit line, it is easy to provide high integration of memory cells.
Because of the bit line formed by the n.sup.+ type diffusion layer, however, the following problems would arise:
(1) As the bit line is isolated from the substrate by a pn junction, the capacity of the bit line is large or the capacity of the pn junction is large. This results particularly in a reduction in the speed of an electrical signal traveling through the bit line, slowing the operational speed. Further, the large bit line capacity drops the potential of a minute electric signal flowing across the bit line. This conventional DRAM is not suitable for larger scale integration (16M, 64M, 256M, 1G, . . . ).
(2) Since the isolation of the bit line from the substrate is realized by the pn junction, there is a large junction leak current flowing from the bit line to the substrate. That is, the pn junction reverse current is large. Accordingly, the potential of a minute electric signal flowing across the bit line is likely to change, reducing the reliability, and the conventional DRAM is not suitable for larger scale integration which will surely be realized.
(3) Due to the isolation of the bit line from the substrate by the pn junction, this DRAM has a low resistiveness to a soft error. There is a high probability of .alpha. rays or the like entering particularly the bit line or a high probability of catching carriers ionized by .alpha. rays or the like, so that noise is likely to appear the bit line. In addition, the carriers entering the bit line may easily cause a malfunction (soft error), thus reducing the operational reliability.